1. Field of the Invention
The present invention relates to a circuit and method for protecting circuit data of a programmable gate array from being copied.
2. Description of the Related Art
A gate array such as an FPGA (Field Programmable Gate Array), in which a circuit configuration is rewritable by a user, is adopted to develop devices in a short period of time and mass-produce them. A circuit data used for the configuration is often stored in a storage device such as a ROM (Read Only Memory), and the FPGA is provided with SRAM (Static Random Access Memory) cells as a program device. It is necessary to copy the circuit configuration data from the ROM into the SRAM cells for programming the FPGA at every start-up such as power-on. This is because a data held in the SRAM cells is erased on power-off. For this reason, the circuit configuration data is copied from the ROM into the SRAM cells. In this case, because the ROM can easily be copied by using a ROM writer, the circuit configuration data is subject to unauthorized copying. Parts such as the FPGA and the ROM are easily commercially available. That is, a device formed by the FPGA can be developed in a short period of time but has a risk that the device developed with great resources may easily be copied.
For this reason, various techniques are known for the copy protection of the device using the FPGA. A copy protection system for a programmable gate array is disclosed in Japanese Laid Open Patent Application (JP-P2003-84853A), which is composed of a logic circuit (CPLD) and a programmable gate array circuit (FPGA). The logic circuit (CPLD) is programmed in a factory, and has an initial-state generator, a first sequence generator, and an encoding circuit. The programmable gate array circuit (FPGA) is programmed. The FPGA has a second sequence generator, a third sequence generator, a decoding circuit, and a sequence comparing circuit. The second sequence generator is a replica of the first sequence generator. In this system, an initial state is generated by the initial state generator of the CPLD. The CPLD initializes the first sequence generator to the initial state. Then, the CPLD encodes the initial state by the encoding circuit, and transmits the encoded initial state to the FPGA. The FPGA decodes the encoded initial state by the decoding circuit. The FPGA initializes the second sequence generator to the initial state. The FPGA generates a call sequence by using the third sequence generator, and transmits a call sequence to the first sequence generator and the second sequence generator. The first sequence generator generates a first response sequence based on the initial state and the call sequence. The first sequence generator transmits a first response sequence to the sequence comparing circuit. The second sequence generator generates a second response sequence based on the initial state and the call sequence, and transmits the second response sequence to the sequence comparing circuit. The sequence comparing circuit compares the first and second response sequences. The sequence comparing circuit permits an operation of an FPGA program when the first and second response sequences are identical to each other. In this way, the copy-protection system for the programmable gate array prevents the illegal copying.
Also, a circuit data protecting method for a field programmable gate array provided with a volatile memory is disclosed in Japanese Laid Open Patent Application (JP-P2001-325153A). In this method, a nonvolatile memory is provided outside the field programmable gate array, as a means to write the circuit data into the field programmable gate array. Encoded circuit data has been written in the nonvolatile memory. At the time of power-on, the circuit data is written from the nonvolatile memory into the volatile memory provided to the field programmable gate array. The field programmable gate array decodes the encoded circuit data and writes the circuit data to the volatile memory. Thus, the circuit data is protected.
As described above, in these conventional examples, a copy of the circuit configuration data is prevented by using the ROM for storing the circuit configuration data for configuring the FPGA and giving a special function to the FPGA. For this reason, the conventional examples are not user-friendly.